Testing for Intermittent Faults in Digital Circuits

In this paper we present a few fundamental results related to the problems of characterization and detection of intermittent faults in digital circuits, which, up to now, have been almost totally ignored. This problem is important since in many technologies intermittency is a predominant mode of failure. We first discuss various new classes of fault modes. We then introduce a Markov model for a specific class of intermittent faults dealt with in this paper, which are signal independent and well behaved. We next introduce some of the statistical properties related to detecting intermittent faults, and present results related to test repetition rate, the efficiency of tests, and the relationship between our model and probabilistic automata. We introduce the concept of a fault pattern for characterizing when an intermittent fault is present, and show that permanent faults and the fault-free situation are included as special cases. Hence this model is a significant generalization of previous work. We then show that, in general, no single test sequence will detect all possible fault patterns. Intuitively this implies that to detect an intermittent fault the test sequence must be in synchronization with the occurrence of the fault. We show how to calculate the probability of detection of a test sequence. We indicate a procedure, based upon the d-algorithm, for constructing a test for an intermittent failure. We show that the behavioral effect of an intermittent failure on a circuit may be to increase the number of internal states in the circuit. That is, X/Y is an I/O sequence associated with an n-state m-input machine having an intermittent fault, then the smallest fault-free m-input machine capable of producing this I/O sequence may have more than n states. Index Tenns-Digital circuits, fault diagnosis, intermittent faults, testing.